1 Field of the Invention
The present invention relates to a memory cell having a double gate field effect transistor which exhibits a doped semiconductor body of a first conductivity type into which a source region and a drain region of a second conductivity type are located, and also exhibiting two separately drivable gate electrodes covering the semiconductor area between the source and drain regions, whereby the edge zones of the second gate electrode cover those portions of the semiconductor area lying outside of the first gate electrode and extending up to the source and drain regions, and which also exhibits a multilayer gate insulation separating at least the first gate electrode from the semiconductor body. The same is chargeable with an electrical charge shifting the threshold voltage.
2 Description of the Prior Art
A memory cell of the type generally set forth above is extensively described in the German published application No. 29 18 888, corresponding to U.S. Pat. No. 4,330,850, fully incorporated herein by this reference. The multilayer gate insulation of the double gate transistor comprises a tunnel oxide layer (SiO.sub.2), a silicon nitride layer (Si.sub.3 N.sub.4) lying above the tunnel oxide layer, and an oxynitride layer covering the silicon nitride layer. Located thereon are the two gate electrodes in two polysilicon levels lying above one another. The first gate electrode serves as a so-called memory gate, whereas the second electrode is employed for the production of inversion layers at the boundary surface of the semiconductor body which respectively extend the source and drain regions in the direction towards the first gate electrode. A transistor having such inversion layers is also referred to as an ICT transistor (inversion charge transistor). The storage of a logical information occurs in such a manner that negative charges are agglomerated at the boundary surface nitride/oxide or, respectively, in the nitride due to a positive voltage of sufficient size supplied to the memory gate, the negative charge shifting the threshold voltage of the transistor. The logical information is again erased by an erase method referred to as short channel erase. When reading from the memory cell, a determination is made as to whether or not the threshold voltage is shifted.
In this known memory cell, a selection transistor is provided whose source/drain segment switches the source/drain of the double gate field effect transistor to the assigned source line. The gate terminal of the selection transistor is connected to a selection line (word line). This, however, means a greater expense of semiconductor surface for the (selectable) memory cell, since it is constructed as a socalled two-transistor cell.